1. Field of the Invention
The present invention relates to the level shifter and, more particularly, to a level shifter for high-voltage level conversion.
2. Description of Related Art
Level shifters are generally applied for low voltage signal to high voltage signal conversion. For example, a large scale liquid crystal display (LCD) requires 20 to 40V signal to turn on thin-film transistors (TFTs) but an input signal applied to the LCD Driver IC is 3V. In this case, a level shifter is applied for the voltage conversion.
FIG. 1 is a circuit of a typical level shifter. As shown, the level shifter includes two PMOSs 11, 12, two NMOSs 13, 14 and an inverter 15. The sources of the PMOSs 11, 12 are connected to a node 16 for providing with an external high voltage HVDD. The sources of the NMOSs 13, 14 are connected to a node 17 for providing with an external low voltage VSS. The drains of the PMOS 11 and NMOS 13 are connected to a node ND1 while the drains of the PMOS 12 and NMOS 14 are connected to a node ND2. Also, the node ND1 is connected to the gate of the PMOS 12 while the node ND2 is connected to the gate of the PMOS 11. In addition, an output terminal OUT is connected to the node ND 1, and an input terminal IN is connected to the gate of the NMOS 14 and also to the gate of the NMOS 13 through the inverter 15. As such, input control signals from the input terminal IN can control the PMOSs 11 and 12 and the NMOSs 13 and 14 on/off, and accordingly the output terminal OUT outputs the high voltage HVDD or the low voltage VSS.
For meeting low input voltage (such as 3V) and high output voltage (such as 40V), the NMOSs 13, 14 typically are high-voltage devices. To achieve this, width/length ratio W/L for the NMOSs 13, 14 is raised while that for the PMOSs 11, 12 is lowered. However, the drain capacitance on the NMOSs 13, 14 becomes more as the W/L is raised too high, and the operating current becomes smaller as the W/L of the PMOSs 11, 12 is lowered. Such a way causes longer transition time on a level shifter and more power consumption.
Further, since the NMOSs 13, 14 have to use high-voltage devices, their threshold voltages are higher. If input voltage is reduced to very low, saturation currents on the NMOSs 13, 14 become smaller so that the voltage shifter is more difficult on level transition and circuit design.
FIG. 2 is a circuit of another typical level shifter, which is similar to that of FIG. 1 except that a PMOS 25 between the PMOS 21 and NMOS 23 and a PMOS 26 between the PMOS 22 and NMOS 24 are added as impedance for current limit. However, the NMOSs 23, 24 still require larger area and current limit provided by the PMOSs 25, 26 is limited.
Therefore, it is desirable to provide an improved level shifter to mitigate and/or obviate the aforementioned problems.